RISC-V doesn't have a flags register. This is an actual advantage: Superscalar microarchitecture implementations do not need to keep track of who set what flag.
This was a very conscious, carefully weighted decision, which presents a net win. One decision of many RISC-V designers had to make.
There's better and worse ways for an ISA to do something. For every ISA decision, implementations (small and large) will either benefit or have to work around.
You'll hear a lot of people insist that ISA doesn't matter; they're provably clueless.
One of them being Torvalds, the transmeta guy (also known for Git, and a couple other hobby projects)
Now I tend to fall on your side of this argument, but I have to say I'd like to see the formal proof of cluelessness :)
Having read previous iterations of the same arguments, I've yet to see anything quite that decisive.
A very capable person no doubt, but also one that's well-known to be wrong[0] about topics he is not an expert at.
0. https://www.cosy.sbg.ac.at/~clausen/PVSE2006/linus-rebuttal....
No one can master these three fields all at once. No one. Not even Linus (who would be a master software developer + a decent compiler specialist).
Which, by the way, includes mention of much attention these few important instructions (not extensions) got.
There is no problem because checking overflows doesn't in practice cause significant overhead, especially in the kinds of superscalar CPUs that are in mobile devices and laptops and PCs and servers these days. Most of the time those wide OoO CPUs are looking in vain for more parallelism. Adding a few overflow-checking instructions just gives them something to do with execution slots they otherwise often can't use.
If there is a actual problem -- which needs to be PROVEN not just hand-waved -- then analyse it in the real world, document it, propose an ISA extension that would actually make things better in real-world applications, not just some hand-picked tiny loop or function.