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A comment on A DRAM Failure. Parent comment
And all of them need to be so perfect that a billion single cells are refreshed, read and written every few ns.
It's very normal that sometimes a ram module breaks.
That's the reason why ECC exist.
ECC also exists btw for bit flip from space radiation.
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And all of them need to be so perfect that a billion single cells are refreshed, read and written every few ns.
It's very normal that sometimes a ram module breaks.
That's the reason why ECC exist.
ECC also exists btw for bit flip from space radiation.