The keyword to research here is ILP (Instruction Level Parallelism) - https://en.wikipedia.org/wiki/Instruction-level_parallelism

There are a whole bunch of factors involved (as pointed out in the above link and by others in this thread) but the basic idea is to parallelize instructions using both Processor Micro-architectural and Compiler techniques i.e. how to get more done in a single clock cycle aka IPC (Instructions Per Clock cycle).