> The cache hierarchy [...] are completely hidden at the level of assembly too

A quick glance at Intel's Software Developer's Manuals [0] falsifies this:

>> TLB and Cacheability control: CLFLUSH, CLFLUSHOPT, CLWB, INVD, WBINVD, INVLPG, INVPCID, and memory instructions with a non-temporal hint (V/MOVNTDQA, V/MOVNTDQ, V/MOVNTI, V/MOVNTPD, V/MOVNTPS, V/MOVNTQ, V/MASKMOVQ, and V/MASKMOVDQU).

> [..] speculative execution are completely hidden at the level of assembly too

Section 18.1.13 specifically mentions side-channels for speculative execution, and there are more than 100 other matches for "speculative" across the document (some of which also refer to load barriers).

So no, these things are not completely hidden at the assembly level, and at least in the case of the (or one of the?) most popular consumer CPU architecture in the world, they are actively documented in the primary reference for an assembly programmer.

[0] https://www.intel.com/content/www/us/en/developer/articles/t...

This is true even on later PDP-11 models with memory caches.

You're much more likely to get bitten by those 2 things at the ASM level... I guess.

So I don't work at that level, I'd love to hear more. What situations do they leak through in?

you'll mostly notice performance problems if you're not aware of cache lines when writing concurrent software, though it's relevant whenever you read from main memory. As for speculative execution, you probably won't really encounter issues related to that unless you go out of your way to. I don't believe it can actually cause problems in programs (though it is helpful for exfiltrating otherwise secret data).