Re:What's new for RISC-V in LLVM 15
by JonChesterfield on Wednesday September 21, 2022 @08:28AM
(#32924039)
A compiler is a pipeline with different representations between each stage. Each representation makes different trade offs, e.g. source tries to be human readable. Translation between them is usually lossy, and that's sometimes a feature - discarding information later stages don't need makes them faster.
Relocations are instructions executed by the linker (or loader). Write the address of this symbol to this offset from the start of the data section, stuff like that. Relaxations cover things like a branch target turned out to be closer than it might have been so change the instruction sequence to a smaller/faster one.
So if you don't eagerly convert to machine code, you don't need the link time relocation data, so the assembler and linker don't need the code to deal with it.
Of course if you stay in a friendly IR you can also do optimisations easily at link time, so most articles on this approach call it 'link time optimisation'.
Re:What's new for RISC-V in LLVM 15
by Joker_vD on Wednesday September 21, 2022 @10:03AM
(#32925313)
Also, see "Global Register Allocation at Link Time" by David W. Wall. An amazing paper, but you can't help to notice that it would have been a much, much easier if he didn't insist on producing valid object files that could be linked together into a working program by a "standard" linker; but he does and so has to resort to linker relaxation too.
I am not a compiler expert but this notion that there are optimisations to be had in the more expressive higher-level compiler IR and then delaying the emitting of machine code rings true. I would be grateful were anyone able to direct me to some papers etc on the subject.