Anyone here ever try using this for only place and route, while sticking to the proprietary tools for synthesis and bitstream generation? I'm honestly not even sure how you'd start (generate xdc and edif in vivado, convert to more common formats, and somehow get timing information?). I get the impression a lot of emphasis is put on bitstream generation when it comes to open source fpga stuff. However, it seems like that's probably not where the real gains are for build time in any production system. Especially since there's no OSS supporting bitstream generation for the highest end boards anyway.