This doesn't exactly come as a surprise. It was already obvious from the desktop parts that something had gone horribly wrong. There just weren't any bright spots there.

Worse single-threaded performance despite much larger cores (even counting each "module" as two "cores" rather than two "threads"). No improvement in clock speeds despite a newer design an deeper pipelines. No improvement in multi-threaded workloads core-for-core. And it seems hard to give credit for the improved multi-threaded performance per-socket, given the huge increase in both transistor count and die size.

It would really be interesting to know what actually went wrong. The new process? The rumored switch to automated design methodology? Unfortunately the answer to the question posed by the article seems obvious... They had to persevere with this and ship it, since they didn't have the resources for a plan B.