> On the other hand, most of 12-series CPUs contains them :-(

E cores in Alder Lake are not listed as vulnerable to this attack.

> as microcoded execution is much simplier and make sense for these cores

Say what? Can you explain what you are basing that on?

If you build a simple, lower-end chip, you do so by giving it fewer hardware resources - fewer things where the implementation is via gates. That means that, in order to implement the same instruction set, you have to implement more via microcode.

I think that's what's being referred do. Microcoded execution is much simpler in terms of the hardware that you have to implement.

>"If you build a simple, lower-end chip, you do so by giving it fewer hardware resources - fewer things where the implementation is via gates."

I'm not following this doesn't the microcode control the gates?

I have a distinct feeling that neither of them have even the slightest clue what they are talking about. If they did understand processor design and had seen pages like this[0], they’d realize that a Goldmont cpu is not dramatically different from a other Intel cores and “microcoding” had virtually no bearing on “why it’s cheaper to make”. The real reasons it’s cheaper:

- only three instruction decoders

- max IPC of 3

- no AVX, AVX2, AVX512

- vector registers are limited to 128bit

- generally tops out below 2ghz as base clock with turbo boost into the mid 2s at best

- very basic integrated GPU on non-server versions running at 200-600mhz

Less registers, less IPC, lower clock frequencies, and less execution units = cheaper cost.

So explain how microcode had something to do with that again?

[0] https://web.archive.org/web/20210117163607/https://www.extre...

> Microcoded execution is much simpler in terms of the hardware that you have to implement.

That’s contrary to everything I’ve ever heard.

Lets take it to extreme: you need very little resources (transistors) to implement Turing Machine, but providing enough microcode (which is very simple structure on silicon - it is ROM, which is trivial and very dense comparing to complex logic) you could emulate any complex ISA on this machine.

For real world example, you could have divider as very complex logic device or as small patch of ROM implementing "school" algorithm in terms of (hardware implemented) additions, shifts and subtractions.

> For real world example, you could have divider as very complex logic device or as small patch of ROM implementing "school" algorithm in terms of (hardware implemented) additions, shifts and subtractions.

Can you show one example of a commercially produced general purpose CPU that does that, let alone a fairly mainstream x86_64 one? In a purely theoretical sense, what you say is plausible, but in the “real world” it’s simply not done.

It was done that way in the original 8086/88: https://www.reenigne.org/blog/8086-microcode-disassembled/

(its successor the 80186 already had a divider in hardware)

I guess I wasn’t explicit, I meant something made in the past decade or two. Going back to 3 decades ago, there’s a handful I can think of, going back almost a half century like the 8086/88, there were even more.