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A comment on RISC-V announces first new specifications of 2022 adding to 16 ratified in 2021. Parent comment

Re:RISC-V announces first new specifications of 2022 adding ... by bpye on Tuesday June 21, 2022 @03:16PM (#31827917)
Whilst true for multiply, divide is considerably more complex. You have to step up to the M3 to get a divide instruction on the ARM side. This is why the new Zmmul is valuable over the existing M extension.
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Re:RISC-V announces first new specifications of 2022 adding ... by monocasa on Tuesday June 21, 2022 @03:24PM (#31828028)
Agreed, but the point was that state machine, iterative, blocking pipeline stages are pretty common even in RISC cores, including particularly ascetic RISC-V and ARM cores. But I can get how at ~12k gates you don't even want the slowest iterative divide unit.
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