When we say that a CPU is running at some frequency that's essentially the speed at which a signal propagates through all the gates of its slowest pipeline stage, and the individual gates have a transition frequency an order of magnitude higher.
So if a CPU is running at 4GHz, it completes a clock cycle in 0.25ns (250ps), but that means that individual transistors must have latencies <=0.025ns (25ps). If you built a tiny little 9-neuron single-layer network out of those transistors then the network's latency would be around the single-gate latency and it would appear to be 20x better than this photonic setup, and even if those 9 neurons were laid out sequentially it would outperform this photonic chip by 2x.
Now granted, that's comparing the performance of a mature IC process using equipment that cost billions of dollars to set up, to something that was built in a university lab on a substantially smaller budget, so direct performance comparisons aren't exactly fair in that sense. But it's also misleading to take a direct hardware implementation of an itty bitty neural network and handwave away the very real issues with scaling such an approach.
That doesn’t limit the creation of new models and new understanding. Just because scaling might be different doesn’t mean it’s impossible.
Our existing models did not exist at some point in the past.
These are not exactly high res images.