It scales linearly with clock speed.
https://blog.stuffedcow.net/2012/07/ivy-bridge-power-consump...
https://qph.cf2.quoracdn.net/main-qimg-61820a6b86759c354d41d...
I said "power consumption increases exponentially with clock speed" not "power consumption increases exponentially with f". That any modern processor has to crank up V to crank up its clock speed is a given.
Hence, power consumption is exponential with clock speed (which is achieved by cranking up both V - the polynomial term in P – and f).
(Which, fine, if you want to be pedantic, is polynomial growth, but that changes nothing about the point, which is that you have to burn a shitload more power at 5 GHz than at 3.2 GHz, because your consumption isn't scaling anything close to linear).
Eh, that's part of it, but a lot of it has to do with the M1 having very very high IPC (much higher than comparable x86-64 parts), meaning they could run the chip at a much lower max clock speed (3.2 GHz versus boosting to 5 GHz for most competitive x86-64 CPUs) for similar overall performance.
This makes a huge difference because power consumption increases exponentially with clock speed.
edit: thinking about how it relates to Intel's process–architecture–optimization, it feels a bit tricky to compare. Apple's process seems to be something like: architecture(A-series chip for iPhones)-optimize-with-new-die-reusing-basic-cores-in-diff-arrangement-targetting-perf-in-small-thermal-envelope(M1 for iPad Pro and small Macbooks)-optimize-again-with-another-new-die-reusing-basic-cores-but-in-yet-another-arrangement-targetting-perf-in-a-wider-thermal-envelope(M1 Pro/Max/Ultra), and that all happens before you get to the next M-series increment, which begins with an A-series increment.
So the M2 is less the optimization of the M1 than it is the re-use of the cores in the new A-series chip preceding it, which was an architectural change, plus optimizations and other SoC differences.