Re:India reveals RISC-V CPU roadmap, expects product by 2023
by avianes on Wednesday May 04, 2022 @06:36AM
(#31258656)
Little addendum:
Macro-op fusion (alone) does not only reduce the number of uop, it could also reduces physical register usage as intermediate results are not stored into physical registers.
For instance, the indexed load pattern (ADD+LOAD) without macro-op fusion needs:
- 2 physical registers in read;
- 2 physical registers in write (one per macro-op), meaning that 2 physical registers will be allocated.
While the macro-op fused version needs:
- 2 physical registers in read;
- 1 physical register in write, meaning that a single physical register will be allocated.
Yes but a high-end core does not necessarily splits instruction the same way as RISC-V does.
For instance an indexed store:
RISC-V ISA splits it into an ADD+STORE pattern which may be recognized by macro-op fusion, while a high-end core splits it into a store_address uop (that compute the effective address and update the address field into the store-buffer entry) and a store_data uop (that update the data field into the store-buffer entry, and this uop is "address agnostic")