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Re:Smaller chips, bigger packages, even bigger headaches (2021) by evancox100 on Thursday April 07, 2022 @10:38AM (#30944981)
They may be making a finer point here, I’m not an expert on packaging, but generally speaking there are packaging processes that support using only “known good die”. You still have the issue of testing the final integrated product, so the packaging process itself needs to have high yield.

For more info check out Dylan Patel’s series on advanced packaging:

https://semianalysis.substack.com/p/advanced-packaging-part-...

https://semianalysis.substack.com/p/advanced-packaging-part-...

https://semianalysis.substack.com/p/advanced-packaging-part-...

Or this from SemiWiki for a shorter overview of just TSMC processes:

https://semiwiki.com/semiconductor-manufacturers/tsmc/290560...

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