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A comment on MIPS provides highly scalable RISC processor IP. Parent comment

Re:MIPS provides highly scalable RISC processor IP by yjftsjthsd-h on Wednesday April 06, 2022 @08:00PM (#30939006)
If you wanted that, couldn't you make a RISC-V chip with a custom extension to add that as a handful of extra instructions?
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Re:MIPS provides highly scalable RISC processor IP by lizardactivist on Thursday April 07, 2022 @04:19AM (#30941997)
Not sure, I'm not read up on RISC-V, but I don't know if someone would want it since AFAIK two's complement means fewer logic gates and a slimmer instruction set.

One's complement arithmetics don't break in the few odd cases like two's complement do though, so there could be that.

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