VRoom A high end RISC-V implementation

Re:VRoom A high end RISC-V implementation by Taniwha on Tuesday March 22, 2022 @05:32PM (#30771845)

If you don't synchronise it's not an issue :-) but if you have 100+ instructions in motion at any one time creating a bottleneck at the end of every basic block would likely have a big effect on how things run.

Normally we retire up to 8 instructions per clock - merging 8 bits of sticky state is some simple logic (some or gates, it doesn't matter what order they get processed in), merging 8 saved PCs (which one do you save?) is harder, it probably means a priority encoder (order probably does matter) and a 63 bit mux (still doable in a clock though)

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Re:VRoom A high end RISC-V implementation by throwaway81523 on Wednesday March 23, 2022 @12:49AM (#30775067)

Ah, well, you're better equipped than I am to figure this out. Anyway the FPU will have to deal with it. Maybe if the big float computations are mostly vector ops, though, that will help.

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