Lanai, the mystery CPU architecture in LLVM

Re:Lanai, the mystery CPU architecture in LLVM by classichasclass on Monday March 21, 2022 @03:30PM (#30758629)

There are many great Power mnemonics. VSX introduced one nearly as good, xxlxor (which, quite reasonably, is a logical XOR between VSX registers/FPRs). It's delightful to try to even pronounce.

The best part is that eieio's derivation is totally plausibly serious from its stated function. (Remember, IBM doesn't have a corporate sense of humour.) It's also an easy, fairly lightweight speculation barrier apart from its official usage.

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Re:Lanai, the mystery CPU architecture in LLVM by thebester5 on Monday March 21, 2022 @06:18PM (#30760439)

My favorite PPC instruction is darn. It delivers a random number, either raw or NIST conditioned. We decided to use the same instruction name in an internal RISCV implementation, and fun times have been had complaining about the darn instruction not working.

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Re:Lanai, the mystery CPU architecture in LLVM by exikyut on Tuesday March 22, 2022 @05:21AM (#30764140)

After mumbling "x-x-l-x-o-r" my brain decided to pronounce it "excelsior". Huh.

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