VRoom A high end RISC-V implementation

Re:VRoom A high end RISC-V implementation by Taniwha on Monday March 21, 2022 @03:06PM (#30758328)

It's likely too big for those programs - I am (just now) starting a build with the Open Lane/Sky tools not with the intent of actually taping out but more to squeeze the architectural timing (above the slow FPGA I've been using for bringing up Linux) so I can find the places where I'm being stupidly unreasonable about timing (working on my own I can't afford a Synopsys license)

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Re:VRoom A high end RISC-V implementation by tsmi on Monday March 21, 2022 @03:20PM (#30758521)

Gotcha. Did you run into any issues with yosys given that it has limited system verilog support?

Ibex needed to add a pass with sv2v https://github.com/lowRISC/ibex/tree/master/syn

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Re:VRoom A high end RISC-V implementation by Taniwha on Monday March 21, 2022 @04:08PM (#30759069)

I'm just starting this week, I've recently switched to some use of SV interfaces and it does not like arrays of them - sv2v seems the way to go - but even without that yosys goes bang! somethings too big Vivado compiles the same stuff - I rearchitected the bit that might obviously be doing this but no luck so far.

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Re:VRoom A high end RISC-V implementation by mithro on Tuesday March 22, 2022 @11:28AM (#30767260)

Checkout Surelog - https://antmicro.com/blog/2020/12/ibex-support-in-verilator-... and the more recent usage in https://github.com/siliconcompiler/siliconcompiler

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