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A comment on Addressing Criticism of RISC-V Microprocessors. Parent comment
ARMv8 and ARMv9 have poor code density. These cache are large as a workaround to that.
This isn't free, as besides making the die larger (and thus lower yields), the L1's clock speed is limited due to its size.
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ARMv8 and ARMv9 have poor code density. These cache are large as a workaround to that.
This isn't free, as besides making the die larger (and thus lower yields), the L1's clock speed is limited due to its size.