Re:Addressing Criticism of RISC-V Microprocessors
by avianes on Sunday March 20, 2022 @03:46PM
(#30745947)
> Go take a look at a lot of C code (hint, look at SPEC benchmarks). They do that.
This does not really justify isolating that snippet if you admit yourself it's a bad one.
> The sins of the original RISC-V was spending too much time looking at RV32 and not realizing how big a problem this is in practice.
But indeed, my previous message shows that even without Zba the problem is erased by a good register allocation and macro-op fusion.
I think you are trying too hard to find special cases that "trick" RISC-V, you didn't even pay attention to the use of unsigned which is non-optimal (unsigned has an undesirable overflow semantic here).
This does not really justify isolating that snippet if you admit yourself it's a bad one.
> The sins of the original RISC-V was spending too much time looking at RV32 and not realizing how big a problem this is in practice.
But indeed, my previous message shows that even without Zba the problem is erased by a good register allocation and macro-op fusion.
I think you are trying too hard to find special cases that "trick" RISC-V, you didn't even pay attention to the use of unsigned which is non-optimal (unsigned has an undesirable overflow semantic here).