Re:Addressing Criticism of RISC-V Microprocessors
by avianes on Sunday March 20, 2022 @03:24PM
(#30745739)
> This biggest issue is one instruction spanning two cache lines
Even with fixed (32 bit) instruction lengths aligned on 32 bit, when we have to decode a group of 8 instructions you are facing this kind of issue.
So you either have to cut the instruction group (and thus not take full advantage of the 8 way decoder) or you have to implement a more complex prefetch with a longer pipeline.
And these special cases can be handled in these pipeline stages.
> It also means you cannot tell instruction boundaries until you directly fetch instructions
I mean, AMD does that on x86, with 14 instruction lengths.
It can be done for RISC-V, it's much cheaper than x86, and it takes significantly less surface area than a bigger cache to compensate.
Even with fixed (32 bit) instruction lengths aligned on 32 bit, when we have to decode a group of 8 instructions you are facing this kind of issue.
So you either have to cut the instruction group (and thus not take full advantage of the 8 way decoder) or you have to implement a more complex prefetch with a longer pipeline. And these special cases can be handled in these pipeline stages.
> It also means you cannot tell instruction boundaries until you directly fetch instructions
I mean, AMD does that on x86, with 14 instruction lengths.
It can be done for RISC-V, it's much cheaper than x86, and it takes significantly less surface area than a bigger cache to compensate.