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A comment on Addressing Criticism of RISC-V Microprocessors. Parent comment

Re:Addressing Criticism of RISC-V Microprocessors by marcosdumay on Sunday March 20, 2022 @11:55AM (#30743718)
The bottleneck on that is data interdependency of your algorithm. If you break it in 6 or 10 instructions, the data dependency stays the same.

(Of course, you can add unnecessary dependency with a badly designer ISA. But it's not a necessary condition.)

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Re:Addressing Criticism of RISC-V Microprocessors by snek_case on Sunday March 20, 2022 @01:05PM (#30744393)
There's still a limit to how many instructions you can decode and dispatch every cycle, even with zero dependencies. There's also definitely dependencies in the example where you're computing a memory address to access a value.
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