Re:RISC-V asm instruction name madness
by wyldfire on Monday March 14, 2022 @11:09AM
(#30673332)
> In the V-extension, they have an instruction named "vrgather".
> But that instruction is not a gather load instruction. This instructoin is just a shuffle instruction.
I don't know that it's the case here but if there's a more general instruction that could do the same effects as another with implicit operands you can preserve the opcode space and create assembler-mapped instructions. So for this case you could make a "vshuffle" mnemonic that encodes a specific vgather with an implied permutation of the inputs. I'm speaking very generally and broadly here - I have no idea about the specifics of the RISC-V vector extension.
> But that instruction is not a gather load instruction. This instructoin is just a shuffle instruction.
I don't know that it's the case here but if there's a more general instruction that could do the same effects as another with implicit operands you can preserve the opcode space and create assembler-mapped instructions. So for this case you could make a "vshuffle" mnemonic that encodes a specific vgather with an implied permutation of the inputs. I'm speaking very generally and broadly here - I have no idea about the specifics of the RISC-V vector extension.