What is interesting is the observation that cost-per-transistor is rising:

"2018 was Apple’s last major step down in cost per transistor due to TSMC’s N10 to N7 process node shrink. With the transition from N7 to N5, the cost benefits were relatively small due to SRAM scaling issues. N7 is entering its 5th year of production, and N5 is now at its 3rd, yet the only hint of per wafer pricing changes have been in the wrong direction... Due to the way the 3 major DRAM companies have slowly increased output, cost per bit of DRAM has not really fallen."

Sophie Wilson (inventor of the original ARM instruction set) has been saying that cost-per-transistor has been rising for several years.

https://www.youtube.com/watch?v=zX4ZNfvw1cw

That's not a new observation, as you mention. However as trailing-edge nodes improve and mature, their cost-per-area should still tend to drop over time. So, in a way, Moore's law might still be full effect despite developments "running ahead of it" at the leading nodes.

Sophie's analysis contemplates a set unit volume and fixed costs related to design and verification and tape out. Mine is on pure cost/transistor based on wafer costs as a player like Apple has the units to spread fixed costs over.

Thanks for the reply, and authoring the article.

I've had several objections to previous comments that cost-per-transistor is rising, and I'm glad to see another confirmation.

It's true that the new core slipped from A15 to A16. The improvements while real were just clock bumps. I'm interested to see if M2 will use the new cores or not.

The IPC gains were what I specifically wrote about and those turned out to be true with <5% IPC gains on the Avalanche core CPU

Look at the in depth analysis I did of the die shot and SOC floorplan. Or even read the article I originally wrote I was right on the CPU architectural gains. Apple pushed clockspeed up slightly, but IPC was less than 5%.

https://semianalysis.substack.com/p/apple-a15-die-shot-and-a...

I wasn't disputing your data point. Indeed, Apple's own provided comparisons indicated that we were going to see smaller IPC gains for the A15 Big core.

I was calling out your analysis. You took the lower than usual IPC gains, and some departures for Nuvia, and surmised that Apple's engineering team must be on the decline and bleeding irreplaceable talent.

It wasn't a terribly unreasonable take given the information at the time before the A15 was even released to the public, but it was pre-mature and a bit hot. Hell that headline was blazing!

When the iPhone 13 actually released, we saw there was much more to the A15 than just pushing pure IPC--the focus for the design was clearly efficiency, and they frankly nailed it. It certainly does not look like the work of an in-decline, listless engineering team.

My original article you are talking about explicitly stated heterogenous compute is the future. It talks about transistor budgets going to LLC, GPU, media, and ISP. Much of the CPU efficiency gain comes from that doubled LLC size.

A15 did falter. Qualcomm just faltered more.

Define falter? When I read anandtech's analysis of the A15, I don't see anything resembling a falter.

A plateau relative to prior generational leaps.

Still vague. Again, if you read the anandtech analysis, nothing indicates a decline in Apple's engineering team, which is what the writer of this story had posited.

https://www.anandtech.com/show/16983/the-apple-a15-soc-perfo...

Maybe he was hired by stock shorters

I don't think there's necessarily ill-intent on the part of the writer. I just think he's missed the mark on some of his past analysis, so I bring some skepticism to anything he writes that goes beyond the facts he has access to.