That cache is not uniform time access. It costs over 100ns to cross the IO die to access another die's L3, almost as much as going to main memory. In practice you have to treat it as 8 separate 32 MB L3 caches.
Also, not everything fits into cache.
At the same time the Threadrippers also have a gargantuan amount of cache that can be accessed at several hundred gigabytes per second per core. Obviously not as nice as being able to hit DRAM at that speed.