Re:Apple M1 Ultra
by paulmd on Tuesday March 08, 2022 @04:47PM
(#30607564)
So now the follow-on question I really wanted to ask: if the CPU can't access all the memory channels does that mean it can only address a fraction of the total memory as CPU memory? Or is it a situation where all the channels go into a controller/bus, but the CPU link out of the controller is only wide enough to handle a fraction of the bandwidth?
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It's more akin to how on Intel, each core's L2 has some maximum bandwidth to LLC, and can't individually saturate the total bandwidth available on the ring bus. But Intel doesn't have the LLC <-> RAM bandwidth for that to be generally noticeable.