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A comment on Clear – Open-Source FPGA ASIC. Parent comment

Re:Clear – Open-Source FPGA ASIC by commandpaul on Wednesday February 23, 2022 @01:00AM (#30438148)
Looks like this has been put together by Efabless themselves. I dont think the rtl would be too different from OpenFPGA(https://github.com/lnis-uofu/OpenFPGA) married to the caravel f/w.
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