Re:Comparing DDR5 Memory from Micron, Samsung, SK Hynix
by sliken on Tuesday February 15, 2022 @10:16PM
(#30355972)
Ah, I didn't know about the lack of variable latency, thanks. Does CXL.mem fix that?
For similar reasons I wish that SSDs, MicroSDs and similar were just stupid devices with simple read/write logic. Then various filesystems, databases, or key/value stores could compete for popularity for things like load leveling, minimizing write amplification, error checking, write performance, IOPs, etc.
Re:Comparing DDR5 Memory from Micron, Samsung, SK Hynix
by bcrl on Wednesday February 16, 2022 @03:08PM
(#30365033)
No vendor wants to sell raw flash without wear leveling that's exposed to software. It's a significant liability from a warranty perspective, as the manufacturer has to potentially replace the device when the user make a mistake or uses poorly written / buggy software that wears out the flash out prematurely. The one place where that does make sense is for hardware devices using SoCs that include interfaces to directly attach NAND flash, but in that case it's usually the hardware vendor that provides the software, leaving random end users out of the loop.
Re:Comparing DDR5 Memory from Micron, Samsung, SK Hynix
by sliken on Wednesday February 16, 2022 @03:11PM
(#30365063)
Dunno, today's warranties often require a tool to verify the drive, which checks the total writes. So if you exceed the lifetime writes you are out of warranty.
Seems trivial to extend that to writes per cell, so if you screw up you lose the warranty.
Now that memory controllers are on the CPU (well, the I/O die for AMD), there's actually a whole lot more slack for the timing needed to do ECC. While the I/O transistors use big, slow transistors for driving the off die signals, the logic is all implemented using the same 3-5+GHz transistors used. This is in constrast to the transistors used in DRAM that are tuned to minimize leakage and are a heck of a lot slower. Putting complicated logic on the DRAM die is a fundamental mismatch with that goal, which encourages DRAM vendors to put the minimum possible logic on their dies. ECC gets better with more logic, and worse with less. Do you really want your DRAM vendor deciding how much ECC is Good Enough for you? I don't.