It's better, but still not the same level of timing guarantees. I suppose, left to right, you would have something like:

SBC/Linux -> SBC/Real-time OS -> General Purpose MCU -> Specialized MCU (Parallax Propeller, for example) -> FPGA/CPLD/DSP

With perhaps some additions to the diagram to account for bit-banging vs actual drivers, speeds where some portion of the left side just isn't fast enough to even kind-of work, slow clock MCUs vs fast clock MCUs, etc.

There are also some some hybrid SOCs, like TI's Sitara chips that the Beagleboard is built around, that have a ARM core for linux, then a couple MCU cores for doing fast-ish realtime stuff. (TI's FAQ says a four instruction busyloop that just toggles a pin can run at about 50MHz on a PRU)

The problem is, machine code is not the lowest level, there is also processor microcode. Machine code doesn't give you a hard real-time guarantee, the execution is still too approximate. FPGA enables you to work on/below the microcode level.