Re:Silicon die teardown: a look inside an early 555 timer chip
by mikebco on Monday January 24, 2022 @01:17PM
(#30061582)
What kind of chip layout/validation tools and methods would have been used for this chip? The layout does not appear to be as dense or uniform as other chip images that I've seen. Is the large spacing between elements more indicative of a prototype that would have been refined later in production?
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Re:Silicon die teardown: a look inside an early 555 timer chip
by kens on Monday January 24, 2022 @01:30PM
(#30061799)
The chip was designed in 1971, so layout would have been drawing it on a large piece of paper and then cutting the masks out of sheets of plastic (Rubylith).
The layout looks typical for that era. Keep in mind that this is an analog chip, so resistors take up a lot of space. Also, with just 24 transistors, you don't need to squeeze every bit out of the layout. I've looked at other versions of the 555 timer and the layout isn't much better. Even the CMOS 555 has a lot of wasted space.