Oh yea, if not for emulating the PDP-11, processor designers would have no interest in instruction level parallelism.

This article is pretty funny actually:

> On a modern high-end core, the register rename engine is one of the largest consumers of die area and power. To make matters worse, it cannot be turned off or power gated while any instructions are running

Yea, let's just gate off the RAT. What's it for again?