Re:Compiling code into silicon
by artisanspam on Wednesday December 08, 2021 @12:04AM
(#29481434)
This isn't a compiler. All this is is a build tool that calls compilers in the background. So benchmarks for this tool aren't really useful.
However, for benchmarks between actual FOSS SystemVerilog compiler front-ends (i.e. language parsing), I've found this[1] chart from CHIPS Alliance to be useful.
Some of the tools listed are parsing + synthesis (yosys) or front-end + simulator (icarus, verilator). Several are just parsers.
However, for benchmarks between actual FOSS SystemVerilog compiler front-ends (i.e. language parsing), I've found this[1] chart from CHIPS Alliance to be useful.
Some of the tools listed are parsing + synthesis (yosys) or front-end + simulator (icarus, verilator). Several are just parsers.
[1]: https://chipsalliance.github.io/sv-tests-results/