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Re:MyHDL: Using Python as a hardware description and verific... by FPGAhacker on Friday November 26, 2021 @07:25AM (#29349624)
For rtl there doesn’t seem to be much reason to use things like hardcaml and chisel.

Testing is usually where the claimed advantage is. That and being open source.

But as you say, SV is all about testing and verification. But the tools are closed source and expensive.

I think the big win is the open source tooling that comes along with these efforts.

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