In the end, on the most constrained workflows, one would have to verify first the python/HDL code using MyHDL, then verify the generated VHDL using the industry tools, then go through the synthesis and place and route processes, add some verification layers there then test the result.
Convincing a team to accept such a framework takes time and organization.
I actually really like Tcl, I like the simplicity of its command argument nature.
The thread "Why is Tcl syntax so weird" was posted a couple of weeks back, https://news.ycombinator.com/item?id=29143346. The first comment on the page includes "Tcl is still a wonderful language and I often lament how itβs mostly died out". Happily, for me at least, it's still going strong in HDL land :)
Brainfuck is stupidly simple but good luck writing reliable code with that!
I should make a TCL quoting quiz to prove how insane it is.
I guess Tcl is just one of things that divides opinion.
The one thing I'll give it is that the "function bodies are just eval'd strings, quoted using braces" is a kind of neat trick for implementing functions. Like if you want to make a language that supports functions with the minimum amount of code possible, that's a fun idea.
Not a good idea, but a fun one. The correct response is "ha that's a neat trick. Now please delete it and do it properly."
Just the fact that it's capable of translating to VHDL or Verilog makes it very useful. I'm surprised the industry doesn't care too much still.