I worked at Intel designing tools for hardware people to use (I am also a hardware person, but I see the power of software) and it was years of hair pulling to get anywhere, even in the face of clear advantages being offered.
Why isn't there an open source simulator as powerful as vcs out there? Why don't we have open source timing analysis tools? Because the culture just doesn't encourage exploration in these areas. And if you try, people will just not take you seriously.
We could argue about the current state of tooling for Clash and its ability to work together with vendor-specific tools and other ecosystem stuff, I don't know much about this. But as a language Clash can do everything Verilog does.
The person you're responding to isn't an FPGA dev (or at least not primarily). They're talking about verilog for ASIC design where the last step is is making the lithography mask that "tapes off" parts of the silicon substrate (like a painter tapes parts of a wall when painting).
I play in the space (Chisel and FIRRTL and CIRCT) so I agree with you but you're being far too dismissive of the people you're aiming to convert.
>But as a language Clash can do everything Verilog does.
Ironic since people say the exact same thing of Haskell and eg python and yet we still don't have wide Haskell adoption.
You have to deeply internalize that a PL or HDL is a tool. Thus, this position makes zero sense
>its ability to work together with vendor-specific tools and other ecosystem stuff, I don't know much about this
No one uses tools that don't fit somehow into their workflow. Further, if the users of the tool are happy with their current toolset then you have a very hard road to hoe in convincing them to adopt your tool.
When I am close to tapeout and I am moving a single gate across a flip flop in order to extract the final few Mhz out of the design, and my formal equivalence checker only understands Verilog, I will have to use Verilog.
I suppose my benchmark in assessing the capabilities of this -or any- language and its ecosystem is the following : Can you use Clash in the design of a reasonably complex chip from scratch (HDL to tapeout)?