https://europractice-ic.com/wp-content/uploads/2020/11/Gener...
...and also happens to be one of the cheapest, at 300 euros/mm^2. This was the highest-density process in the early 90s and used for CPUs such as the 486 and Pentium.
Like I can use a 1/8" router bit to make a 1/8" wide channel, or I can use that same router bit to make a 1" wide channel. I know these machines don't use routers but I don't really understand why they can't create larger features if they can create smaller ones.
I suspect they can.... but maybe its just not cost-effective. Why use a 5nm process to create a 180nm feature-size chip, when you can use a 180nm process for 99% less cost.
If I'm wrong please correct my misconception!
Chips aren't 2D structures, they're built out of 3D layers and all those layers have a constant thickness.
But like what if you did it anyway? I remember pondering this while looking at some guitar pedal schematics. A lot of them use ICs that are basically ancient. Do newer processes have anything to offer (even if it wouldn’t be cost-efficient)?
It is different with power electronics. There often you have to provide a certain amount of power to actually move something, or make a motor turn, or make a speaker make sound, etc. So the amount of current and/or voltage your chips produce will actually matter.
Say you have a guitar amp. What if someone told you that at a great cost, they could make the chips at that amp a hundred times smaller. They would of course provide a hundred times less power which would make your speaker a hundred times more quiet (well, 2 db, but you get the idea). Would that be a good deal? Not really.
That is why analog and power firms like ON Semi (mentioned in the article) tend to look for old equipment. They do not need everything this small. Many of their chips actually require larger features because they have to move a lot of current and/or handle high voltages.
But that does not mean that their chips are old technology. Not all innovation is making things smaller. There is plenty of innovation going at the larger sizes.
First, you are very likely "pad limited", the pads to connect the chip to the package are much larger than the actual active chip area.
Second, newer processes are rarely better at analog-type things. Leakage is worse, noise is worse, etc. Generally, you have to add to the transistor "length" (minimum dimension) in order to get back analog performance parameters.
Third, newer processes have to run at really small power supply voltages. Old-school metal gate CMOS in 0.5um or larger was good to 18V+--really good for things like guitar pedals.
If you have the tools, you'd be better off doing a guitar pedal in a very old technology.
I remember doing the maths for this a while ago, and I believe on a 22nm process you could fit an entire 486 (1.2M transistors) in the area of a single bond pad needed for the later CPUs.
The parent poster probably refers to BBD delay lines such as the MN3007 and similar devices, whose awful fidelity and noise characteristics made them famous and very recognizable in old music, especially from the 70s. Emulating them in digital is doable, but that requires more complex circuitry. If one could fit a BBD delay line and its clock generator, plus a LFO and a few low noise opamps on the same die, it would be possible to create delay based (echo/flanger/phaser/chorus etc.) pedals at extremely low costs.
A chip that fits its package comfortably at 180nm will not benefit from converting it 5nm process at all.
The main reasons to get with a smaller process node is to put more transistor on the same area, use less power or reduce the size of the chip, that's it. A power management chip does not qualify.
There is one more reason: if you are already invested in smaller process node or when it is difficult to find machinery for older process.
https://www.theverge.com/tldr/2021/3/2/22309412/nasa-perseve...
Of course this isn't a problem most of us will ever deal with but I still think it's interesting.
Power savings would pale in comparison to cost and for many components like amps, bigger = more power.
Making larger wafers drives prices up, because the process of making a monocrystal larger and larger, but I don't think that's a major cost factor except for super cheap chips. The minimum cost of a 200mm wafer is about $2/in^2 and the minimum cost for a 300mm wafer is about $3/in^2, in case that's helpful.
* Shrink the average node size 1-2 times (E.G. 180nm to 90 or 45nm)
* Combine popular combinations of products into a single package that can have interlinks cut by laser or skipped at the metal traces stage?
* Generally consolidate similar products within fewer variations?
The slightly greater cost of the physical wafer is supposed to be offset by the increased machine throughput and the die shrinks possible, as well as ideally fewer defects by using newer processes. An extremely inexpensive set of processes for 300mm wafers would also be a good target for long term bulk semiconductor production.
Masks are not a significant expense for most processes. Nor is the bare wafer. It is all the process steps that drive the cost.
300mm qafer
Are there reliability or ruggedness concerns where some use cases prefer older processes?