OK, I'll admit I'm confused here. I thought nMigen was a kind of Python-to-Verilog compiler. (I know Migen was a separate HDL; I'm not exactly sure the relationship between Migen and nMigen.) Something about your comment has me questioning whether that's correct.

Is there a tool that does what I'm describing? I assumed that a Python-to-Verilog or VHDL compiler would be useful if you could find ways to map concise Python syntax to slightly more verbose HDL constructs. That'd give you Python's expressiveness, but maintain compatibility with a bunch of vendor toolchains if you could emit something commonly supported like verilog-2001.