Disagree with the answer to the first question on sizing. Resistive model doesn't seem appropriate for CMOS transition, the MOSFET will spend most of the time in saturation, so you don't need to upsizes gates just because they're in series. (The real answer in a modern process node is that parasitics dominate, and you need to simulate the design with the extracted parasitics from the layout. But I get that it's just an academic exercise.)