Re:Practice Problems for Hardware Engineers
by JoachimS on Thursday October 14, 2021 @09:00AM
(#28863660)
Not so sure. There are questions related to pipelining, combinational tree loads, retiming etc. For backend ASIC stuff this is valuable things to know and understand. I would say quite a few of the material are quite far from trivial.
If SW people are asked to build linked lists, reversing tree structures etc, I would assume these questions for EEs, CSEEs would be asked too. I know I've asked similar things in the past.
If SW people are asked to build linked lists, reversing tree structures etc, I would assume these questions for EEs, CSEEs would be asked too. I know I've asked similar things in the past.