From FPGA design point of view SystemVerilog is OK. I think it gives high enough level of abstraction to create even complex systems. It can also be readable after some years if care is taken to keep the code clean.

But I believe we need LISPy syntax - mainly for simplicity, also for easier parsing and static analysis. I think LISP is a natural way to describe data flow. Unfortunately none of the attempts to write functional synthesizable code that I found so far make the code simpler.

BTW I'm preparing a talk on simplifying RTL code. Can I cite some of your posts in this thread?