AMD Demonstrates Stacked 3D V-Cache Technology: 192 MB at 2 TB/SEC

Re:AMD Demonstrates Stacked 3D V-Cache Technology: 192 MB at... by linuxftw on Tuesday June 01, 2021 @11:44AM (#27356285)

> Now what we have over the years seen interest in is adding processing cores to the RAM itself and maybe having a small dedicated processor for some tasks attached to the RAM may well prove viable.

I think we call these 'GPUs' today.

> just a row of slots you addedd a module that had CPU/RAM

As you mentioned, GPUs fit this description, but some PCIe devices are full-blown embedded systems.

I think we're at the point where the only major improvements will take place on the CPU die itself.

[ Parent | on HN ]

Re:AMD Demonstrates Stacked 3D V-Cache Technology: 192 MB at... by derefr on Tuesday June 01, 2021 @01:23PM (#27358109)

GPUs aren't quite the same, because they're (mostly) SIMD. GPUs don't have the independent per-compute-core memory bandwidth required for every core to be running its own execution thread with an independent instruction pointer, independent data fetches, and (especially) non-correlated branch-prediction failures / cache misses. (This is most of the reason that branching, if even implemented in the GPU's ISA, is effectively useless.)

Whereas, what the parent poster is describing would be true MIMD: a bunch of tiny cores each with its own on-board RAM, its own instruction pointer, and then a bus (or a bunch of busses) fast enough to feed them all data from (probably NUMA) main memory.

GPUs don't provide any advantage for running e.g. a high-concurrency Erlang application server. But a true-MIMD system would.

[ Parent | on HN ]