SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

Re:SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7... by snypher on Friday April 16, 2021 @10:07AM (#26834058)

"The tape out means that the documentation for the chip has been submitted for manufacturing to TSMC, which essentially means that the SoC has been successfully simulated. The silicon is expected to be obtained in Q2 2021."

Would this mean the actual chip delivery may still be delayed?

[ Parent | on HN ]

Re:SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7... by StringyBob on Friday April 16, 2021 @10:24AM (#26834258)

Chip manufacturing has many steps. For a new leading edge process it may take 3-6 months to get silicon back after submitting the design to a silicon foundry for manufacturing.

For a small volume ‘shuttle’ run hopefully there won’t be delays, but this is not the same as having working chips!

The foundry will do initial checks it is manufacturable at ‘tapeout’ when you submit your design, but you don’t know for sure if your chip works with intended functionality until you get it back! You are relying on lots and lots of simulations up front before your ‘tape-out’.

Sometimes issues are found and a chip requires a re-spin - basically another go with the bugs fixed. You want to do this as few times as possible (ideally right first time) due to cost and time of these iterations.

[ Parent | on HN ]