Glacial – Microcoded RISC-V core designed for low FPGA resource utilization

Re:Glacial – Microcoded RISC-V core designed for low FPGA re... by starkruzr on Saturday March 20, 2021 @10:40PM (#26527711)

so RISC-V has been around for decades, right? why does it seem like it's blowing up now?

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Re:Glacial – Microcoded RISC-V core designed for low FPGA re... by pjscott on Saturday March 20, 2021 @10:57PM (#26527776)

The RISC approach to microprocessor design has been around since the 1980s, but the specific instruction set called "RISC-V" has only been around since 2010.

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Re:Glacial – Microcoded RISC-V core designed for low FPGA re... by _chris_ on Saturday March 20, 2021 @11:02PM (#26527793)

It takes years for tooling to improve and for industry designs to start making it out into the world. As more designs make it into end-users' hands, the tooling has even more motivation to improve.

I feel like that slow evolution can make it appear "suddenly popular" despite being around for a few years. =)

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Re:Glacial – Microcoded RISC-V core designed for low FPGA re... by brucehoult on Sunday March 21, 2021 @06:49PM (#26534887)

Design work was started on RISC-V in 2010 and an initial frozen spec was released to the public in 2015. The first proper 32 bit chip and board (HiFive1/FE310) shipped in December 2016, and the first Linux-capable 64 bit chip and board (HiFive Unleashed/FU540) in April 2018.

It's pretty new.

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