It might be nice to have a README section that compares your project with existing alternatives, such as Ragel: http://www.colm.net/open-source/ragel/

I've used Ragel before for many parsers and a handful of state machines -- however, it's a bit awkward for a "pure" state machine. Makina looks interesting though, I will take a deeper look.

BTW: If anyone remembers Zed Shaw, he wrote some interesting stuff on using Ragel as a state machine for his Utu protocol:

http://web.archive.org/web/20090214182920/http://www.zedshaw...

Yes thanks for the tip that's something I'll be working on.

Looks very nice. Seems like a good fit, potentially, for structuring some complex systems' code.

Thanks for sharing it.

Thanks!

graphical and VHDL output would be very nice.

I intend to work on a graphical output.