They work better primarily because they had previously invested in the tooling to rad-harden them and it’s really expensive to do that again one time for each mission; cheaper to rely on already-rad-hardened designs.

Not necessarily; physical size matters a lot.

Just an example: consider you were to add some extra electrical charge to the gate of a transistor (from an electron or ion beam, I don't know).

A larger transistor has a higher gate capacitance, it is therefore quite immune against a few extra charges. On smaller transistors, though, it could dramatically increase the voltage, leading to a bit error, or destroying the transistor. Capacitance in this case is proportional to the area.

Higher density also has some inherent drawbacks against particles, since a damaged part is proportionately more damaged if it is smaller.

More ancient processes are also higher-voltage, and higher-current, so they can handle a lot more noise on these signals.

This raises the question, why not simply continue to make larger circuits today for this purpose?

Surely we could still make a chip today with the same transistor size as one from 2001, but better in other ways.

I believe the reason is that volume is too low. The radiation hardened chips for Curiosity and Perseverance are variants of Power chips made by BAE. I am surprised though that they have not released any newer chip in time for Percy. There is a newer generation, the 5500, but I believe it was not ready for Percy. Percy uses the same chip as Curio.

That's one way of doing it. But making bigger integrated circuits (IC) is hard. And it wouldn't automatically give you increased performance.

In microelectronics, costs are directly proportional to the die area. Actually, they might rise faster due to yield issues.

Making masks [1] is expensive. The bigger the mask, the more expensive. A mask set for a modern CPU can easily be in the millions, I think. And it gets more expensive with size.

Then you have yield. The bigger the chip, the more likely it has some defects (due to dust or other issues during fabrication). Often, processes work more or less well across a wafer: temperature higher in the center, etc. That can affect performance.

Due to yields, bigger chips have to be scrapped more often, and are generally less performant. Binning (selecting the fastest, slowest, more efficient, or chips with specific intact features across a wafer) is less effective. You might have to add redundancy or mechanisms to cut power to damaged areas to avoid short circuits.

Now, that's why we don't generally make bigger integrated circuits. Now, we could make bigger integrated circuits with today's latest clean rooms and equipment to try to raise yields. I don't know if that's being done already, but it would likely raise costs. On the other hand, progress is being made on bigger chips as well [2].

Another more promising direction (IMO) is to use chiplets like AMD does it. You could use more of these for a bigger virtual size.

Now, like I wrote, a lot of the performance improvements actually come down from physically scaling down the transistors: if the gate is smaller, the transistor needs less electrons to charge up. That means faster transistors, and less energy. Also, transistors are closer, so signals reach the next one faster [3].

If you want bigger chips at a previous technological node, you are going to need a huge heatsink, or disable part of the chip ("dark silicon") [4].

The real answer might come from completely different architectures, based on light or spin, or more power-efficient circuit/computer architectures like with adiabatic computing [5] (or non von neumann based, closer to what I do).

Power efficiency is key, since that's the limiting factor for performance nowadays (ask any overclocker: you don't want to melt your CPU. Also, rovers have a small energy budget). With better efficiency, you have room to grow performance again.

Paradoxally, software seems headed in the other direction, generally speaking.

[1] https://en.wikipedia.org/wiki/Photomask

[2] https://news.ycombinator.com/item?id=20739408

[3] https://en.wikipedia.org/wiki/Dennard_scaling

[4] https://en.wikipedia.org/wiki/Dark_silicon

[5] https://en.wikipedia.org/wiki/Adiabatic_circuit

Doesn't radiation mostly cause random one-off errors rather than permanent defects? If so, then if the rad-harden stuff is 100x slower (which I think is approximately right?), it is almost certainly better to use error correction on non-rad-hardened hardware.

In addition to SEUs (single event upsets) which are bit flips, there are also the following Single Event Effects (See) that are destructive:

- Single Event Burnout, SEB

- Single Event Gate Rupture, SEGR

- Single Event Latch-up, SEL these can be recoverable

In addition there are also Total Ionizing Dose (TID) Effects https://radhome.gsfc.nasa.gov/radhome/tid.htm

Sure, no doubt they occur. But at what rate?

Many types of bit error are not recoverable without a full system reset. It isn't a matter of a simple "this bit in ram got corrupted", but more "this floating point unit has got into a state where it will not produce a result, and will therefore hang the entire processor".

Therefore boot time becomes critical - if you end up rebooting due to bit errors multiple times per second, you can't afford to wait for Linux to start up each time...

Run 9 systems in parallel and reset the ones that give less common results or no results at all.

You still have 10% the surface area, power usage and weight and 10 times the speed of the radiation hardened ones.

And that’s why it’s wise to have multiple systems running at the same time, if one errors you still hopefully have another online. There’s a reason airplanes and now cars are designed this way. I’m sure they’re working towards this too.

Well I suppose they do not have to load all the kernels and drivers that Linux provides today.

I wonder how one could use micro kernels to further improve startup time and have a mini distributed OS/kernel for each component.

This is a problem with floating point operations happening at a lower level than the error correction you're imagining. In principle, that's not at all necessary. Are you arguing that it's infeasibly expensive to design a chip with operations that are error correctable?

It's possible - but you'll end up reinventing nearly every step of the IC design process, which will cost a lot.

These projects also have long development periods, they want to be sure everything works so they can't just sub things out at the last minute. So you end up with a system using 10 year old tech.

Will be interesting when missions are being launched utilising the tech of today, like rad hardened neuromorphic chips https://www.businesswire.com/news/home/20200902005406/en/Bra...

Non-mobile link: https://en.wikipedia.org/wiki/Radiation_hardening

Can't all of the radiation issues be mitigated with proper shielding of the electronics?

Yes, but the problem is that radiation shielding is heavy because it's typically made of lead.

https://media.ccc.de/v/36c3-10575-how_to_design_highly_relia... is a really interesting talk by some guys from CERN who have to design chips for use in particle accelerators and other physics experiments where they must survive unusually hostile radiation environments.

It's trickier than it seems because some forms of radiation can induce different kinds of radiation when they hit the dense shielding so you're kind of back to square one in that you still need a radiation resistant processor.