I've personally created a BSP and did board bring-up on a platform based on the NXP LS1046A (one of their ARM based QorIQ SoCs). That chip uses DDR4 and didn't require any blobs (aside from the Ethernet hardware). All of the memory controller registers were fully documented too. The DDR4 controller there was very similar to the DDR3 controller on their older T2080 PPC chip that I've worked with.
In fact, one of the most annoying parts of the board bring up was determining what data strobe delay values to use via a process of trial and error.
I'm not sure why NXP would use a different DDR4 controller for the iMX that requires a blob while their other chips don't.
I've confirmed the presence of these blobs in i.MX8M BSPs myself, as has Purism, see their blog post.
https://github.com/u-boot/u-boot/blob/master/arch/arm/mach-i...
I don't know whether RK3399 uses Synopsys. There are other DDR4 PHY IP providers, like Cadence, which don't require firmware.
I wonder how I could have missed that issue with the Librem 5 till now.
> Probably the most notable SoC containing a Synopsys DDR4 memory controller and PHY is the NXP i.MX8M series, which was for example selected by Purism to form the heart of their Librem 5 phone.
Is this (still) true? I just tried to find any binary blobs in U-Boot source tree [0], but didn't find any.
At least for some Rockchip SoCs (RK3399), which I assume also use Synopsys IP DDR PHYs, I know that it's not necessary to provide anything else apart from upstream U-Boot and Arm Trusted Firmware (ATF) [1]. And AFAICT current mainline U-Boot can initialize NXP i.MX8M's DDR PHY, too.
[0] https://gitlab.denx.de/u-boot/u-boot
[1] https://stikonas.eu/wordpress/2019/09/15/blobless-boot-with-...