Re:We Test PCIe 4.0 Storage: The AnandTech 2021 SSD Benchmar...
by numpad0 on Tuesday February 02, 2021 @03:29AM
(#25998534)
The version of explanation I have read is that it's SLC cache getting saturated(same deal as CMR cache region in DM-SMR except read/write can parallelize), and that it won't happen with enough cache amount and fast, parallel writes, so explanation differs but solution sounds right
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