Re:Again on 0-based vs. 1-based indexing
by jdsully on Wednesday January 20, 2021 @05:45PM
(#25852968)
Verilog and other HDL languages work this way, its not an accident humans would start this way as well as the natural world works in parallel.
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Re:Again on 0-based vs. 1-based indexing
by Jtsummers on Wednesday January 20, 2021 @06:00PM
(#25853079)
I actually started writing a comment about that. Teaching VHDL (my experience) to most programmers is an entertaining experience because they expect effects to be immediate, not executed collectively and simultaneously but mediated by a clock or other mechanism. So in an HDL:
x <= y;
y <= y * 20;
These two effects actually occur simultaneously, which is different again from what mathematically inclined learners might expect since there is still mutation. It is more akin to the common notation: x' = y
y' = y * 20
Where the ' indicates the next value of x or y (as opposed to the derivative). Or perhaps: x_n = y_{n-1}
y_n = y_{n-1} * 20
And many programming languages don't even have a good notion for similar parallel evaluation and assignment. Python does, with: x, y = y, y * 20
Common Lisp has psetf which permits this: (psetf x y
y (* y 20))
Languages with pattern matching/destructuring bind are your best bet for writing this directly without needing temporary variables.