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A comment on Memory access on the Apple M1 processor. Parent comment

Re:Memory access on the Apple M1 processor by wtallis on Wednesday January 06, 2021 @08:42PM (#25666150)
> One can measure where the bottlenecks are, and it's rare to find that the front-end is the bottleneck.

Part of this is due to the fact that x86 processor designers won't include more execution units than they can feed from their instruction decoders. Apple's processors are much wider than x86 on both the decode and execution resources, and it's pretty clear that the M1 would not perform as well if its decoders were as narrow as current x86 cores.

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Re:Memory access on the Apple M1 processor by nkurz on Wednesday January 06, 2021 @09:30PM (#25666559)
> it's pretty clear that the M1 would not perform as well if its decoders were as narrow as current x86 cores

This would imply that it's able to sustain ILP greater than 4 (or maybe 5 with macro-fusion). Does it actually manage to do this often? If so, that's really impressive. I was guessing that most of the advantage was coming from the improved memory handling, and possibly a much bigger reorder buffer to better take advantage of this, but I'm happy to be shown otherwise.

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