I just read the answer as well. It's not "embarrassing", but it basically doesn't answer the question. Instead, it argues that the question is equivalent to asking what's the point of Python vs. C.

So in the end, the answer doesn't provide any specific answer regarding SystemVerilog and Chisel. All I found is one mention of negotiating parameters, which Verilog doesn't do. I would have loved to hear a lot more about examples of what Chisel makes more convenient than SystemVerilog.