Re:An Open-Source FPGA-Optimized Out-of-Order RISC-V Soft Pr...
by nickik on Tuesday January 05, 2021 @09:27AM
(#25645801)
There are tons of people using System Verilog for RISC-V. The majority of work done is with System Verilog and not Chisel. Having lots of cores in both Chisel, System Verilog and many other languages (VHDL,BlueSpec and so on) is a huge benfit for RISC-V
SiFive values programmability above everything and for that Chisel is pretty clearly an advantage.
SiFive values programmability above everything and for that Chisel is pretty clearly an advantage.